1. Field
This disclosure relates generally to semiconductor device packaging, and more specifically, to a mechanism to reduce localized stress in the area of electrical interconnects under a packaged device die.
2. Related Art
In certain types of semiconductor device packaging, semiconductor device die contacts are electrically coupled to a package substrate interconnect. Traditional methods of forming this coupling involve a solder reflow operation using solder bumps or solder-tipped metal columns formed on contacts of the semiconductor device die to contacts on the package substrate interconnect. These methods involve heating at least the contact region to temperatures sufficient to cause the solder to flow.
Issues have arisen in recent packaging development work on semiconductor die having lead-free solder bumps or solder-tipped metal columns, in which semiconductor die inter-layer dielectric delamination occurs under the bumps or metal columns, known as white bumps or ghost bumps on large die/large packages. Delamination is a particular issue for semiconductor die using low-k and ultra-low-k dielectrics (e.g., films composed of silicon, carbon, oxygen, and hydrogen—SiCOH films) that tend to be more brittle due to their increased porosity. This delamination occurs, in part, due to differences in the coefficient of thermal expansion between the semiconductor device die material and the package substrate material. As the different materials cool down subsequent to solder reflow, a high stress occurs in the interconnect region, resulting in the delamination.
It is therefore desirable to provide a mechanism for electrically coupling a semiconductor device die to a semiconductor device package substrate that avoids introduction of excessive temperature induced stresses to the semiconductor device die interconnect.
The use of the same reference symbols in different drawings indicates identical items unless otherwise noted. The figures are not necessarily drawn to scale.